1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory including a mask ROM, an OTP, an EPROM, an EEPROM, and a FLASH memory which simultaneously achieves high speed information reading and a high degree of integration and a method for reading data from the non-volatile semiconductor memory.
2. Description of the Background Art
Non-volatile semiconductor memories realize most highly integrated memory LSIs by using a single transistor as a memory cell (herein after a memory cell transistor). As a standard method for storing information, the threshold voltage of the memory cell transistor is changed in accordance with the information. In the case of the EPROM and FLASH memory, the threshold voltage of the memory cell transistor is changed by changing the amount of electrons charged in the floating gate. In the case of the mask ROM, the threshold value of the memory cell transistor is changed by adjusting the concentration of impurities such as phosphorus or boron introduced in a channel region.
Corresponding to desired functions and performances of each type of memory LSI to be realized, many types of systems coexist for a memory cell matrix configuration for arranging multiple memory cell transistors in the row and column directions, a matrix driving circuit for selecting a memory cell transistor corresponding to a read address within the memory cell matrix, and an information detecting circuit for judging whether the selected transistor is conductive or not and outputting the information. In what follows, prior arts related to each of these three items will be explained.
According to the conventional memory cell matrix configuration, sources and drains of multiple memory cells are connected to each pair of adjacent column lines to form a column arrangement, and multiple row lines are connected commonly to the gates of the memory cells of each of the column of the column arrangement. This configuration can achieve the highest degree of integration and does not have any diffusion layer, which is a high resistance material, on the current path for reading information stored in the memory cell. Therefore, this configuration is suitable for high speed non-volatile semiconductor memories having a high degree of integration.
However, if this configuration is used to form a memory cell matrix having a large area, the resistance of the metal line material that constitutes the column line cannot be ignored. To cope with this problem, each of the column lines is divided to form sub-bit lines. A selection transistor constituted of a transistor that differs from the memory cell is then provided for each divided unit. This selection transistor is connected to a low resistance main bit line made of another metal line. This method is disclosed in the Japanese Patent Application Laid-Open No. 2565109. The memory cell matrix configuration disclosed in this Japanese Patent Application Laid-Open will be hereafter called an inter-column arrangement type memory cell matrix configuration.
Next, the conventional matrix driving circuit for the inter-column arrangement type memory cell matrix configuration will be explained. As described in the Japanese Patent Application Laid-Open No. 2565104, according to the inter-column arrangement type memory cell matrix configuration, non-selection memory cells on a selected row line can be conductive. Therefore, all the memory cells on the selected row line can be conductive under the worst condition.
According to the read operation of the inter-column arrangement type memory cell matrix disclosed in the Japanese Patent Application Laid-Open No. 2565104, 2-bit information is read simultaneously from the memory cell. A ground potential GND is applied to the column line connected to the memory cell that is simultaneously read. Thus, a read current flows corresponding to the data read from the memory cell. A data read circuit then identifies and outputs the read current. On the other hand, the electric potential difference between those columns connected to unread memory cells is set to a very small value, causing little amount of current to flow. As a result, little amount of leak current flows from the column lines connected to the unread memory cells. Thus, the data read speed is prevented from being reduced.
Lastly, the conventional information detection circuit will be explained. Installed in the non-volatile semiconductor memory disclosed in the Japanese Patent Application Laid-Open No. H3-13675 is a circuit which applies a relatively high electric potential, for example, 1V to the memory cell matrix, and detects the inflow current while applying a relatively low electric potential, for example, 0.2V to the selected column line. According to this configuration, it is possible to set to 1V the electric potentials of the source and drain of the non-selection memory cells connected to the row lines. As a result, the load capacitance of the channel unit of the non-selection memory cell as floating capacitance is reduced, and the speed of signal transmission through the row lines can be increased.
However, as an inflow current detection system, only the one applicable to semiconductor integrated circuits having a memory cell matrix of simple NOR configuration constituted of high electric potential lines provided parallel to the row lines and bit lines provided orthogonal to the high electric potential lines was disclosed.
According to the inter-column arrangement type memory matrix configuration, a select transistor that does not share its source or drain with the other select transistors needs to be installed on both sides of each sub-bit line to connect the main bit line with the sub-bit line. Since the memory cell must be formed using transistor columns of the smallest size, the above-mentioned select transistor must be installed on both sides of each array segment providing the same pitch as the transistor columns. However, the select transistor needs to have a large gate width since the select transistor needs a capability to drive a sufficiently large amount of current in comparison with the memory cell.
Moreover, according to the matrix driving circuit of the inter-column arrangement type memory matrix configuration described in the Japanese Patent Application Laid-Open No. 2565104, the circuit for selecting a column line and a column decoder is complicated. Therefore, it is impossible to separate the main bit lines from the sub-bit lines to create a gap having a small area and provide a select transistor for controlling the gap.
Moreover, when an inflow current detection system is applied to the memory matrix having an inter-column arrangement type configuration, the leak between two selected adjacent column lines, which is a problem pointed out in the Japanese Patent Application Laid-Open No. 2565104, turns even more serious since the electric potentials of the drain and source of the non-selection memory cells that cause the leak are low. Therefore, a high impedance cannot be obtained by an inter-column resistance formed by a single memory cell, making it difficult to obtain a sufficiently wide operation margin.